Existing Accelerators

Work in Progress

This page is still a work in progress. More to come soon.

Accelerator Tiles

Tile Type Notes
ASA Key/data associative accelerator NoC glue is in-repo; the ASA compute core itself is an external black box
Cache Direct-mapped, write-back DRAM cache Backs the mesh’s shared-memory (mPut/mGet/mLoad/mStore) address space
FFT Fast Fourier Transform Chisel-generated, single-precision floating point, multiple size/width configs
FP Floating point ALU Adder, multiplier, divider, square root — one tile type each
TSQR Tall-Skinny QR decomposition Chisel-generated Householder-QR pipeline; typically paired with FFT
MoDIN Spiking neuromorphic processor Lives on the modin git branch, not main

Example Testcases

A few pages in this section document testcases rather than standalone accelerator hardware — they combine or stress-test the tiles above:

Testcase Demonstrates
SCF Combined FFT + TSQR pipeline across a 3x3 mesh
Sweep FP adder tile inside a larger 8x8 mesh
Demo Software-only asynchronous triangular solver using the cache tile
SNE  

See the sub-pages for detailed specifications, NoC protocol details, and worked software examples for each.

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